IJAEEE ABSTRACT
| Title | : | Realization Of Multiplier Design With Novel |
| Authors | : | G.S Sankari , G.Sharmila |
| Keywords | : | Adaptive hold logic, razor flip flop, reliable multiplier, variable latency. |
| Issue Date | : | May 2016 |
| Abstract | : | Digital multipliers are the most critical arithmetic functional units. The overall performance of the systems depends on the throughput of the multiplier. At the same time, the negative bias temperature instability effect occurs when a transistor is under negative bias, increasing the threshold voltage of the transistor and reducing multiplier speed. A similar phenomenon, positive bias temperature instability occurs when a transistor is under positive bias. Therefore, it is important to design high-performance reliable multipliers. In this paper, aging-aware multiplier design with novel adaptive hold logic (AHL) circuit is proposed. The proposed architecture can be applied to a column or row bypassing multiplier. The experimental results show that, the proposed architecture with 4 × 4 column-bypassing multipliers and 4 × 4 row-bypassing multipliers. This Adaptive Hold Logic Multiplier is implemented using Verilog HDL and Simulated by Modelsim 6.4c and Synthesized by Xilinx 9.1 |
| Page(s) | : | Pages : 1 -5 |
| ISSN(Online) | : | 2395-3527 |
| Source | : | IJAEEE - Volume 2 Issue 5 |
| : |
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